All the equivalent circuit models of neurons written in an #verilog would be a cool project

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c

[New Blog Post] Comparing Two Verilog CPU Implementations using EBMC https://www.philipzucker.com/td4_ebmc/ #verilog #formal

Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.

Technical work is often with #rust #kicad #python #verilog #c, and in all-too-rare moments stuff like #haskell #forth #agda and #prolog

I've never been much for social media, usually preferring to keep interests local: a better-detailed #introduction to follow as I figure this out

I will be speaking on Saturday Morning, Jan25th, at the SVFIG meetup about an #FPGA Vector processor. Here is how it does #vector multiplies. Starts at 9:30 am California time. #verilog

http://forth.org/zoom

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

#Xilinx could have had a PERFECTLY FINE VALID-READY INTERFACE if it wasn't for that IMPORTANT note WHY! GAH! #hardware #FPGA #HDL #RTL #Verilog #VHDL

In the mood for the littlest bit of #FPGA #GameDev? Check out this pico-ice based #pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/pong_top.c

Gifted a new #FPGA dev board this season? PipelineC aims to make #hardware description easier for #embedded folks.
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #HLS
https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup

Today's #AdventOfCode part1 was again a surprisingly fast success (anonymous variables in #perl ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (#verilog), and will also have the 10yo learn how to solve it (#python). Thanks a lot to @ericwastl for not ruining Sunday with a 3d falling grid problem!

Did You Know YoSys Knows VHDL Too? - We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while... - https://hackaday.com/2024/12/04/did-you-know-yosys-knows-vhdl-too/ #verilog #yosys #fpga #vhdl

First steps completed on this years #AdventOfCode pure-hardware challenge (no processor, no software) solution: behavioural #verilog that solves both parts of day 1.
Next step is to implement a hardware bubblesort with registers and a counter, then will replace behavioural model by RTL. I'm not likely to actually get it working on an #fpga ... but I am stupid enough to try.

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice #HDL #Verilog #VHDL #hardware #embedded

My new #Introduction

I am building tiny real-time #Forth co-processors for MicroPython, Circuit Python and RISC-V. On FPGA's a stack machine can be 1/2 the size of a 32 bit RISC-V soft core.

#Forth, #MicroPython #CircuitPython #Riscv #StackMachine #FPGA #Verilog
#realtime

Calling all #HDL hackers! I need help in putting the #MIT #CADR onto a FPGA board. #VHDL, #Verilog, does not matter much. Who is up for a fun challange? #LispMachine

In a better world, #Verilog would have /clk instead of posedge clk, \clk instead of negedge clk, and _clk to mean 'clock is down'.

I'm curious: does anyone know what this synthesizes to, if it's synthesizable at all
Verilator simulates it setting the "out" register 1 clock earlier than non-blocking assignment, but when I run it through Vivado it seems to synthesize it with two registers like non-blocking
#verilog #fpga #hardware