Hm, not happy with SPIR-V to ISA on my RDNA3 that is reordering loads from shared memory in some ways that it is actually slightly less efficient...
Is there a way to instruct the ISA compiler via GLSL to not reorder loads from shared mem? (Not workgroup/subgroup barriers but simple no-reordering) I haven't yet tried if volatile could do the trick
Anyone has some thoughts?